In an Integrated fan-out (InFO) wafer, a plurality of dies are embedded in a material (such as molding compound), at two or more locations horizontally or vertically separated from each other. Interconnects between dies are formed in one or more redistribution layers (RDL) above the dies. Using this technology, copper interconnects formed after the exposure of on-chip aluminum pads, known as post-passivation interconnects (PPI), allow signals to fan out to regions larger than the silicon die footprint. I/O's can be redistributed to the fan-out region outside of the silicon die footprint for increased pin count at the package or wafer level. Passive devices such as inductors and capacitors can be formed over the molding compound for lower substrate signal loss and higher electrical performance. A smaller form factor leads to better thermal behavior and hence a lower operating temperature for the same power budget, or alternatively, faster circuit operation for the same temperature profile.